Differential cache block sizing for computing systems
US11379379B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 30, 2020 |
| Grant date | Jul 5, 2022 |
| Priority date | — |
| Expiry date | Apr 30, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/6028
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Described is a computing system and method for differential cache block sizing for computing systems. The method for differential cache block sizing includes determining, upon a cache miss at a cache, a number of available cache blocks given a payload length of the main memory and a cache block size for the last level cache, generating a main memory request including at least one indicator for a missed cache block and any available cache blocks, sending the main memory request to the main memory to obtain data associated with the missed cache block and each of the any available cache blocks, storing the data received for the missed cache block in the cache; and storing the data received for each of the any available cache blocks in the cache depending on a cache replacement algorithm.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.