Secondary device detection using a synchronous interface
US11379402B2 · kind B2 · utility
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18Claims
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Key dates
| Filing date | Oct 20, 2020 |
| Grant date | Jul 5, 2022 |
| Priority date | — |
| Expiry date | Oct 20, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2213/0002
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A chiplet system can include a Serial Peripheral Interface (SPI) bus for communication. A controller or primary device coupled to the SPI bus can generate a message with read or write instructions for one or more secondary devices. In an example, the primary device can be configured to use information on a data input port or data input bus to determine a communication status of one or multiple secondary devices on the bus.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.