Memory with optimized resistive layers

US11380732B2 · kind B2 · utility

Assignee

• Micron Technology, Inc. · US

Inventors

• Lei Wei · Longbeilingcun, CN
• Pengyuan Zheng · Boise, US
• Kevin Lee Baker · Boise, US
• Efe Sinan Ege · Boise, US
• Adam Thomas Barton · Boise, US
• Rajasekhar Venigalla · Hopewell Junction, US

Key dates

• Filing date: Jul 29, 2020
• Grant date: Jul 5, 2022
• Expiry date: Jul 29, 2040

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10N70/8825

Abstract

A memory system may include separate amounts or types of resistive material that may be deposited over memory cells and conductive vias using separate resistive layers in the access lines. A first resistive material layer may be deposited over the memory cells prior to performing an array termination etch used to deposit the conductive via. The array termination etch may remove the first resistive material over the portion of the array used to deposit the conductive via. A second resistive material layer may be deposited after the etch has occurred and the conductive via has been formed. The second resistive material layer may be deposited over the conductive via.