Ferroelectric memory device
US11380773B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 31, 2019 |
| Grant date | Jul 5, 2022 |
| Priority date | — |
| Expiry date | Nov 22, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D99/00
Abstract
A semiconductor memory device of an embodiment includes a semiconductor layer; a gate electrode including a first portion, a second portion provided to be spaced apart from the first portion, and a spacer provided between the first portion and the second portion; and a first insulating layer provided between the semiconductor layer and the gate electrode and including a first region containing a ferroelectric, a ferrielectric, or an anti-ferroelectric, a second region containing a ferroelectric, a ferrielectric, or an anti-ferroelectric, and a boundary region provided between the first region and the second region. The first region is positioned between the first portion and the semiconductor layer, the second region is positioned between the second portion and the semiconductor layer, the boundary region is positioned between the spacer and the semiconductor layer, and the boundary region has a chemical composition different from that of the spacer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.