Method for fabricating flash memory
US11387241B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 22, 2020 |
| Grant date | Jul 12, 2022 |
| Priority date | — |
| Expiry date | Feb 27, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6892
Abstract
A method for fabricating flash memory is provided. A plurality of floating gate structures is formed on a gate dielectric layer in the memory device region of a substrate. The protective spacers are formed on two opposite sidewalls of each floating gate structure. A polysilicon gate structures are formed on the logic device region and a polysilicon control gate structure with an opening are formed on the memory device region to cover two adjacent floating gate structures, wherein the two protective spacers facing each other between two adjacent floating gate structures are exposed by the opening, and then the exposed protective spacer are removed. An ion implantation is performed on the substrate to form a source region between the two adjacent floating gate structures on each cell area. There will be no polysilicon material residue in the memory device region or pitting/undercutting phenomenon in the logic device region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.