Payload parity protection for a synchronous interface
US11392448B2 · kind B2 · utility
0Cited by
0References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 20, 2020 |
| Grant date | Jul 19, 2022 |
| Priority date | — |
| Expiry date | Jan 14, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4282
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A chiplet system can include a Serial Peripheral Interface (SPI) bus for communication. A controller or primary device coupled to the SPI bus can generate a message with read or write instructions for one or more secondary devices. In an example, the primary device can be configured to read information from a secondary device about whether the secondary device supports parity-protected data communications. The primary device can be configured to selectively send or receive parity-protected data communications depending on a capability of the secondary device to support parity.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.