Circuit and method for at speed detection of a word line fault condition in a memory circuit
US11393532B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 13, 2020 |
| Grant date | Jul 19, 2022 |
| Priority date | — |
| Expiry date | Apr 13, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/1204
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
First and second memory arrays have common word lines driven by a row decoder in response to a row address. A first word line encoder associated with the first memory array encodes signals on the word lines to generate a first encoded value, and a second word line encoder associated with the second memory array encodes signals on the word lines to generate a second encoded value. Comparison circuitry compares the first encoded value to a first expected value (e.g., a first portion of the row address) and compares the second encoded value to a second expected value (e.g., a second portion of the row address). An error flag is asserted to indicate presence of a word line fault based upon a lack of match between the first encoded value and the first expected value and/or a lack of match between the second encoded value and the second expected value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.