Doped polar layers and semiconductor device incorporating same

US11398570B2 · kind B2 · utility

Assignee

• Kepler Computing Inc. · US

Inventors

• Ramesh Ramamoorthy · Moraga, US
• Sasikanth Manipatruni · Ithaca, US
• Gaurav Thareja · Santa Clara, US

Key dates

• Filing date: Apr 7, 2020
• Grant date: Jul 26, 2022
• Expiry date: Apr 7, 2040

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/62

Abstract

The disclosed technology generally relates to ferroelectric materials and semiconductor devices, and more particularly to semiconductor memory devices incorporating doped polar materials. In one aspect, a semiconductor device comprises a transistor formed on a silicon substrate and a capacitor electrically connected to the transistor by a conductive via. The capacitor comprises upper and lower conductive oxide electrodes on opposing sides of a polar layer, wherein the lower conductive oxide electrode is electrically connected to a drain of the transistor. The capacitor additionally comprises a polar layer comprising a base polar material doped with a dopant, wherein the base polar material includes one or more metal elements and one or both of oxygen or nitrogen, wherein the dopant comprises a metal element that is different from the one or more metal elements and is present at a concentration such that a ferroelectric switching voltage of the capacitor is different from that of the capacitor having the base polar material without being doped with the dopant by more than about 100 mV. The semiconductor device additionally comprises a lower barrier layer comprising a refractory meta…