Read refresh to improve power on data retention for a non-volatile memory
US11404127B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 11, 2021 |
| Grant date | Aug 2, 2022 |
| Priority date | — |
| Expiry date | Feb 11, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0483
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory apparatus and method of operation are provided. The apparatus includes memory cells each connected to a word line and arranged in one of a plurality of blocks and configured to retain a threshold voltage corresponding to a data state. The memory cells are operable in one of a first read condition in which a word line voltage is discharged and a second read condition in which the word line voltage is coupled up to a residual voltage level. A control circuit determines a power on event and periodically apply a predetermined refresh read voltage to the word line for a predetermined period of time for each of the plurality of blocks at a specified interval based on at least one data retention factor to maintain the memory cells of the plurality of blocks in the second read condition in response to determining the power on event.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.