Semiconductor packages with thin die and related methods
US11404276B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 20, 2020 |
| Grant date | Aug 2, 2022 |
| Priority date | — |
| Expiry date | Oct 24, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/10156
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Implementations of a semiconductor device may include a semiconductor die including a first largest planar surface, a second largest planar surface and a thickness between the first largest planar surface and the second largest planar surface; and one of a permanent die support structure, a temporary die support structure, or any combination thereof coupled to one of the first largest planar surface, the second largest planar surface, the thickness, or any combination thereof where the semiconductor die may be coupled with one of a substrate, a leadframe, an interposer, a package, a bonding surface, or a mounting surface. The thickness may be between 0.1 microns and 125 microns.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.