Multi-chip packages and sinterable paste for use with thermal interface materials
US11404349B2 · kind B2 · utility
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11Claims
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Key dates
| Filing date | Dec 7, 2016 |
| Grant date | Aug 2, 2022 |
| Priority date | — |
| Expiry date | Dec 7, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/16152
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In some embodiments a semiconductor die package includes a package substrate, a plurality of dies each attached to the package substrate, a layer of a thermally conducting sintered paste over the top of each die, a layer of flexible polymer thermal interface material over the sintered paste, and a heat spreader over and thermally connected to the polymer thermal interface material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.