Patent · US Active

Failure structure in semiconductor device

US11404370B2 · kind B2 · utility

0Cited by

1References

17Claims

0Family size

Assignee

Infineon Technologies AG · DE

Inventors

Thomas Basler · Riemerling, DE
Andreas Huerner · Nuremberg, DE
Caspar Leendertz · Munich, DE
Dethard Peters · Edenkoben, DE

Key dates

Filing date	Nov 27, 2019
Grant date	Aug 2, 2022
Priority date	—
Expiry date	Mar 6, 2040

Classification

Technology area (CPC H)Electricity
CPC primaryH10D62/8325
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

A semiconductor device is provided. In an embodiment, the semiconductor device comprises a control region, a first power region, a second power region, an isolation region and/or a short circuit structure. The control region comprises a control terminal. The first power region comprises a first power terminal. The second power region comprises a second power terminal. The isolation region is between the control region and the first power region. The short circuit structure extends from the first power region, through the isolation region, to the control region. The short circuit structure is configured to form a low-resistive connection between the control region and the first power region during a failure state of the semiconductor device.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.