Self-aligned repeatedly stackable 3D vertical RRAM

US11404482B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Noriyuki Sato · Hillsboro, US
• Kevin P. O'Brien · Cincinnati, US
• Eungnak Han · Portland, US
• Manish Chandhok · Beaverton, US
• Gurpreet Singh · Alwar, IN
• Nafees Kabir · Portland, US
• Kevin Lin · Beaverton, US
• Rami Hourani · Santa Clara, US
• Abhishek A. Sharma · Hillsboro, US
• Hui Jae Yoo · Hillsboro, US

Key dates

• Filing date: Jun 29, 2018
• Grant date: Aug 2, 2022
• Expiry date: Dec 2, 2040

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10N70/8836

Abstract

An integrated circuit structure includes a first material block comprising a first block insulator layer and a first multilayer stack on the first block insulator layer, the first multilayer stack comprising interleaved pillar electrodes and insulator layers. A second material block is stacked on the first material block and comprises a second block insulator layer, and a second multilayer stack on the second block insulator layer, the second multilayer stack comprising interleaved pillar electrodes and insulator layers. At least one pillar extends through the first material block and the second material block, wherein the at least one pillar has a top width at a top of the first and second material blocks that is greater than a bottom width at a bottom of the first and second material blocks.