Low latency post-quantum signature verification for fast secure-boot

US11405213B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Santosh Ghosh · Hillsboro, US
• Vikram Suresh · Hillsboro, US
• Sanu K. Mathew · Hillsboro, US
• Manoj Sastry · Portland, US
• Andrew H. Reinders · Portland, US
• Raghavan Kumar · Hillsboro, US
• Rafael Misoczki · Hillsboro, US

Key dates

• Filing date: Jun 28, 2019
• Grant date: Aug 2, 2022
• Expiry date: Oct 22, 2040

Classification

• Technology area (CPC H): Electricity
• CPC primary: H04L2209/125
• WIPO field: Digital communication
• WIPO sector: Electrical engineering

Abstract

In one example an apparatus comprises a computer readable memory, an XMSS verification manager logic to manage XMSS verification functions, a one-time signature and public key generator logic, a chain function logic to implement chain function algorithms, a low latency SHA3 hardware engine, and a register bank communicatively coupled to the XMSS verification manager logic. Other examples may be described.