Electronic package, manufacturing method thereof and conductive structure
US11410954B2 · kind B2 · utility
0Cited by
2References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 7, 2020 |
| Grant date | Aug 9, 2022 |
| Priority date | — |
| Expiry date | Jul 15, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3651
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Provided is an electronic package, including a first substrate of a first conductive structure and a second substrate of a second conductive structure, where a first conductive layer, a bump body and a metal auxiliary layer of the first conductive structure are sequentially formed on the first substrate, and a metal pillar, a second conductive layer, a metal layer and a solder layer of the second conductive structure are sequentially formed on the second substrate, such that the solder layer is combined with the bump body and the metal auxiliary layer to stack the first substrate and the second substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.