Clock and data recovery circuit
US11411565B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 23, 2020 |
| Grant date | Aug 9, 2022 |
| Priority date | — |
| Expiry date | Dec 23, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/091
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A first sampling circuit takes phase offset first samples of a received serial data stream in response to a first edge of a sampling clock and a first comparator circuit determines whether the plurality of phase offset first samples have a same logic state. A second sampling circuit takes phase offset second samples of the received serial data stream in response to a second edge of the sampling clock, opposite the first edge, and a second comparator circuit determines whether the phase offset second samples have a same logic state. One of the first samples or one of the second samples is then selected in response to the determinations made by the first and second comparator circuits. A serial to parallel converter circuit generates an output word including the selected one of the first and second samples.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.