Rupesh SINGH
17Patents
2h-index
6Co-inventors
39Inventor score
Filing activity: Dec 19, 2017 → Aug 24, 2023
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US10050640B1 | High speed data weighted averaging architecture | Electricity | 6 | Active |
| US10218380B1 | High speed data weighted averaging architecture | Electricity | 4 | Active |
| US10211850B1 | High speed data weighted averaging architecture | Electricity | 2 | Active |
| US11043960B2 | Sigma-delta analog-to-digital converter circuit with correction for mismatch error introduced by the feedback digital-to-analog converter | Electricity | 1 | Active |
| US10862503B2 | Clock jitter measurement using signal-to-noise ratio degradation in a continuous time delta-sigma modulator | Electricity | 1 | Active |
| US11656848B2 | High throughput parallel architecture for recursive sinusoid synthesizer | Electricity | 1 | Active |
| US11094354B2 | First order memory-less dynamic element matching technique | Electricity | 1 | Active |
| US12224414B2 | Method and system for recovery of metals from spent lithium ion batteries | Emerging Cross-Sectional Technologies | 0 | Active |
| US11463098B2 | Method and device for testing successive approximation register analog-to-digital converters | Electricity | 0 | Active |
| US11417371B2 | First order memory-less dynamic element matching technique | Electricity | 0 | Active |
| US11563443B2 | High speed data weighted averaging (DWA) to binary converter circuit | Electricity | 0 | Active |
| US11989148B2 | Data bridge for interfacing source synchronous datapaths with unknown clock phases | Electricity | 0 | Active |
| US12093193B2 | High throughput digital filter architecture for processing unary coded data | Physics | 0 | Active |
| US12086568B2 | High throughput parallel architecture for recursive sinusoid synthesizer | Electricity | 0 | Active |
| US11411565B2 | Clock and data recovery circuit | Electricity | 0 | Active |
| US11092993B2 | Digital sinusoid generator | Electricity | 0 | Active |
| US10484165B2 | Latency buffer circuit with adaptable time shift | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.