Multiple-table branch target buffer
US11416253B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 10, 2020 |
| Grant date | Aug 16, 2022 |
| Priority date | — |
| Expiry date | Aug 23, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/323
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor includes two or more branch target buffer (BTB) tables for branch prediction, each BTB table storing entries of a different target size or width or storing entries of a different branch type. Each BTB entry includes at least a tag and a target address. For certain branch types that only require a few target address bits, the respective BTB tables are narrower thereby allowing for more BTB entries in the processor separated into respective BTB tables by branch instruction type. An increased number of available BTB entries are stored in a same or a less space in the processor thereby increasing a speed of instruction processing. BTB tables can be defined that do not store any target address and rely on a decode unit to provide it. High value BTB entries have dedicated storage and are therefore less likely to be evicted than low value BTB entries.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.