Reset speed modulation circuitry for a decision feedback equalizer of a memory device
US11417374B1 · kind B1 · utility
1Cited by
0References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 18, 2021 |
| Grant date | Aug 16, 2022 |
| Priority date | — |
| Expiry date | Mar 3, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4093
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and methods described herein provide decision feedback equalizer (DFE) circuitry that includes one or more phases. The one or more phases receive bit feedback at respective inputs of the phases. The DFE circuitry also may include variable reset circuitry. The variable reset circuitry may reset voltages of the bit feedback at inputs of each of the phases. The variable reset circuitry is configured to change its reset frequency between resets.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.