Optical routing structure on backside of substrate for photonic devices
US11417596B2 · kind B2 · utility
1Cited by
0References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 4, 2020 |
| Grant date | Aug 16, 2022 |
| Priority date | — |
| Expiry date | Nov 18, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG02B2006/12107
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
In some embodiments, the present disclosure relates to an integrated chip that includes an insulator layer arranged over a substrate. Further, an upper routing structure is arranged over the insulator layer and is made of a semiconductor material. A lower optical routing structure is arranged below the substrate and is embedded in a lower dielectric structure. The integrated chip further includes an anti-reflective layer that is arranged below the substrate and directly contacts the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.