Transistor device with a varying gate runner resistivity per area

US11417747B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Thomas Aichinger · Faak am See, AT
• Wolfgang Bergner · Waldbüttelbrunn, DE
• Ralf Siemieniec · Villach, AT
• Frank Wolter · Munich, DE

Key dates

• Filing date: Oct 16, 2020
• Grant date: Aug 16, 2022
• Expiry date: Nov 3, 2040

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/2527

Abstract

In an example, a transistor device is provided. The transistor device includes a plurality of transistor cells each including a gate electrode and each at least partially integrated in a semiconductor body that includes a wide bandgap semiconductor material. The transistor device includes a gate pad arranged on top of the semiconductor body, and a plurality of gate runners each arranged on top of the semiconductor body and each connected to gate electrodes of at least some of the plurality of transistor cells. Each gate runner of the plurality of gate runners has a longitudinal direction, and at least one of the gate runners includes at least a section in which a resistivity per area increases in the longitudinal direction as a distance to the gate pad along the gate runner increases.