Three dimensional perpendicular magnetic tunnel junction with thin film transistor array
US11417829B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 18, 2018 |
| Grant date | Aug 16, 2022 |
| Priority date | — |
| Expiry date | May 18, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N50/85
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A three dimensional magnetic random access memory array that includes a sourceline formed on a substrate and a magnetic memory element pillar that includes a plurality of magnetic memory element pillars formed over the substrate. The three dimensional magnetic random access memory array also includes a transistor formed between the magnetic memory element pillar, the transistor being functional to electrically connect the sourceline and magnetic memory element pillar. A plurality of magnetic memory element pillars may be formed over the substrate with a transistor between each memory element pillar to selectively connect or disconnect each of the magnetic memory element pillars. The transistor can include an epitaxial semiconductor structure having a gate dielectric formed at a side of the epitaxial semiconductor and a gate material formed on the gat dielectric such that the gate dielectric material is between the gate material and the semiconductor material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.