Efficient retention flop utilizing different voltage domain
US11418174B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 30, 2021 |
| Grant date | Aug 16, 2022 |
| Priority date | — |
| Expiry date | Apr 30, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/356078
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A system and method for efficiently retaining data in sequential elements during power down modes. In various embodiments, a master latch of a flip-flop circuit receives an always-on first power supply voltage, whereas, a slave latch and other surrounding circuitry receives a second power supply voltage capable of being powered down. During a power down mode, circuitry consumes less power while the master latch retains stored data. In some designs, the flip-flop circuit is a level shifting circuit, and the always-on first power supply voltage is less than the second power supply voltage. The master latch uses complex gates with a p-type transistor at the top of a stack of p-type transistors receiving the always-on power supply voltage level on its source terminal and the retained data value on its gate terminal. This top p-type transistor is capable of remaining disabled even when used in a level shifting manner.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.