Greg M. Hess
40Patents
5h-index
34Co-inventors
65Inventor score
Filing activity: Nov 17, 2005 → Sep 27, 2023
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US8860464B2 | Zero keeper circuit with full design-for-test coverage | Physics | 9 | Active |
| US7834662B2 | Level shifter with embedded logic and low minimum voltage | Electricity | 9 | Active |
| US7411409B2 | Digital leakage detector that detects transistor leakage current in an integrated circuit | Physics | 7 | Expired |
| US11005459B1 | Efficient retention flop utilizing different voltage domain | Electricity | 6 | Active |
| US8912853B2 | Dynamic level shifter circuit and ring oscillator using the same | Electricity | 5 | Active |
| US9529533B1 | Power grid segmentation for memory arrays | Emerging Cross-Sectional Technologies | 5 | Active |
| US7454674B2 | Digital jitter detector | Physics | 5 | Active |
| US8014211B2 | Keeperless fully complementary static selection circuit | Physics | 5 | Active |
| US8570788B2 | Method and apparatus for power domain isolation during power down | Physics | 4 | Active |
| US10523194B2 | Low leakage power switch | Electricity | 4 | Active |
| US7995410B2 | Leakage and NBTI reduction technique for memory | Physics | 4 | Active |
| US8558603B2 | Multiplexer with level shifter | Electricity | 4 | Active |
| US8102728B2 | Cache optimizations using multiple threshold voltage transistors | Physics | 3 | Active |
| US8174918B2 | Passgate for dynamic circuitry | Physics | 2 | Active |
| US7994820B2 | Level shifter with embedded logic and low minimum voltage | Electricity | 2 | Active |
| US9286971B1 | Method and circuits for low latency initialization of static random access memory | Physics | 2 | Active |
| US9236100B1 | Dynamic global memory bit line usage as storage node | Physics | 1 | Active |
| US8203898B2 | Leakage and NBTI reduction technique for memory | Physics | 1 | Active |
| US10453505B2 | Pulsed sub-VDD precharging of a bit line | Physics | 1 | Active |
| US8476930B2 | Level shifter with embedded logic and low minimum voltage | Electricity | 1 | Active |
| US11418174B2 | Efficient retention flop utilizing different voltage domain | Electricity | 1 | Active |
| US9131899B2 | Efficient handling of misaligned loads and stores | Physics | 0 | Active |
| US9207705B2 | Selectable phase or cycle jitter detector | Electricity | 0 | Active |
| US9455000B2 | Shared gate fed sense amplifier | Physics | 0 | Active |
| US12333357B2 | Memory bit cell for in-memory computation | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.