Operational code storage for an on-die microprocessor
US11422826B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 19, 2020 |
| Grant date | Aug 23, 2022 |
| Priority date | — |
| Expiry date | Oct 24, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/7211
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods, systems, and devices for operational code storage for an on-die microprocessor are described. A microprocessor may be formed on-die with a memory array. Operating code for the microprocessor may be stored in the memory array, possibly along with other data (e.g., tracking or statistical data) used or generated by the on-die microprocessor. A wear leveling algorithm may result in some number of rows within the memory array not being used to store user data at any given time, and these rows may be used to store the operating code and possibly other data for the on-die microprocessor. The on-die microprocessor may boot and run based on the operating code stored in memory array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.