Memory array staircase structure
US11423966B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 27, 2020 |
| Grant date | Aug 23, 2022 |
| Priority date | — |
| Expiry date | Oct 27, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D88/01
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Routing arrangements for 3D memory arrays and methods of forming the same are disclosed. In an embodiment, a memory array includes a first word line extending from a first edge of the memory array in a first direction, the first word line having a length less than a length of a second edge of the memory array perpendicular to the first edge of the memory array; a second word line extending from a third edge of the memory array opposite the first edge of the memory array, the second word line extending in the first direction, the second word line having a length less than the length of the second edge of the memory array; a memory film contacting the first word line; and an OS layer contacting a first source line and a first bit line, the memory film being disposed between the OS layer and the first word line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.