Fabrication process comprising an operation of defining an effective channel length for MOSFET transistors
US11424342B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | Jul 27, 2020 |
| Grant date | Aug 23, 2022 |
| Priority date | — |
| Expiry date | Aug 12, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/83
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In fabricating metal-oxide-semiconductor field-effect transistors (MOSFETs), the implanting of lightly doped drain regions is performed before forming gate regions with a physical gate length that is associated with a reference channel length. The step of implanting lightly doped drain regions includes forming an implantation mask defining the lightly doped drain regions and an effective channel length of each MOSFET. The forming of the implantation mask is configured to define an effective channel length of at least one MOSFET that is different from the respective reference channel length.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.