Stacked die chip package structure and method of manufacturing the same
US11430768B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 23, 2021 |
| Grant date | Aug 30, 2022 |
| Priority date | — |
| Expiry date | Feb 23, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A chip package structure includes a wiring board, a first chip, a second chip, a thermally conductive material, a molding compound and a heat dissipation part. The wiring board includes a plurality of circuit pads. The first chip is mounted on the wiring board and is electrically connected to at least one of the circuit pads. The first chip is located between the second chip and the wiring board. The thermally conductive material is located on the wiring board and penetrates the second chip and the first chip to extend to the wiring board. The molding compound is disposed on the wiring board, and the heat dissipation part is disposed on the molding material and thermally coupled to the thermally conductive material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.