3D NAND memory device with select gate cut
US11430811B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 21, 2021 |
| Grant date | Aug 30, 2022 |
| Priority date | — |
| Expiry date | Jan 21, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/31144
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A memory device includes a stack of alternating word line layers and insulating layers over a substrate. The word line layers includes a bottom select gate (BSG) positioned over the substrate. The memory device includes first dielectric trenches that are formed in the BSG of the word line layers and extend in the length direction of the substrate to separate the BSG into a plurality of sub-BSGs. The memory device also includes a first common source region (CSR) that is formed over the substrate and extends in the length direction of the substrate. The first CRS further extends through the word line layers and the insulating layers in a height direction of the substrate, where the first CSR is arranged between two adjacent first dielectric trenches of the first dielectric trenches.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.