Enhancement of yield of functional microelectronic devices
US11435393B2 · kind B2 · utility
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16References
18Claims
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Key dates
| Filing date | Nov 2, 2018 |
| Grant date | Sep 6, 2022 |
| Priority date | — |
| Expiry date | May 11, 2041 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02P90/02
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Described herein are techniques related to a semiconductor fabrication process that facilitates the enhancement of systemic conformities of patterns of the fabricated semiconductor wafer. A semiconductor wafer with maximized systemic conformities of patterns will maximize the electrical properties and/or functionality of the electronic devices formed as part of the fabricated semiconductor wafer. This Abstract is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.