Avalanche-protected transistors using a bottom breakdown current path and methods of forming the same
US11437466B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 11, 2020 |
| Grant date | Sep 6, 2022 |
| Priority date | — |
| Expiry date | Aug 11, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/126
Abstract
An avalanche-protected field effect transistor includes, within a semiconductor substrate, a body semiconductor layer and a doped body contact region having a doping of a first conductivity type, and a source region a drain region having a doping of a second conductivity type. A buried first-conductivity-type well may be located within the semiconductor substrate. The buried first-conductivity-type well underlies, and has an areal overlap in a plan view with, the drain region, and is vertically spaced apart from the drain region, and has a higher atomic concentration of dopants of the first conductivity type than the body semiconductor layer. The configuration of the field effect transistor induces more than 90% of impact ionization electrical charges during avalanche breakdown to flow from the source region, to pass through the buried first-conductivity-type well, and to impinge on a bottom surface of the drain region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.