Data bus duty cycle distortion compensation
US11442877B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 30, 2020 |
| Grant date | Sep 13, 2022 |
| Priority date | — |
| Expiry date | Oct 30, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0483
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An electrical circuit device includes a signal bus comprising a plurality of parallel signal paths and a calibration circuit, operatively coupled with the signal bus. The calibration circuit can perform operations including determining a representative duty cycle for a plurality of signals transferred via the plurality of parallel signal paths, the plurality of signals comprising a plurality of duty cycles and comparing the representative duty cycle for the plurality of signals transferred via the plurality of parallel signal paths to a reference value to determine a comparison result. The calibration circuit can perform further operations including adjusting, based on the comparison result, a trim value associated with the plurality of duty cycles of the plurality of signals to compensate for distortion in the plurality of duty cycles and calibrating the plurality of duty cycles of the plurality of signals using the adjusted trim value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.