Synthesis of a network-on-chip (NoC) using performance constraints and objectives
US11449655B2 · kind B2 · utility
13Cited by
9References
17Claims
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Key dates
| Filing date | Dec 30, 2020 |
| Grant date | Sep 20, 2022 |
| Priority date | — |
| Expiry date | Jan 21, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2115/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and methods are disclosed that implement a tool for executing performance-aware topology synthesis of a network, such as a network-on-chip (NoC). The tool is provided with network information. The tool uses the network information to automatically determine data width and clock speed for each element in the network that meet the network's constraints and performance requirements. The tool is able to provide the performance-aware topology synthesis rapidly, while honoring the objectives and the network's constraints.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.