Manufacturing method for semiconductor package including filling member and membrane member
US11450535B2 · kind B2 · utility
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3References
4Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 3, 2017 |
| Grant date | Sep 20, 2022 |
| Priority date | — |
| Expiry date | Apr 3, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3025
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package comprising a fan-out structure and a manufacturing method therefor are disclosed. A semiconductor package according to an embodiment of the present invention comprises: a wiring unit comprising an insulation layer and a wiring layer; a semiconductor chip mounted on the wiring unit and coupled to the wiring layer by flip-chip bonding; a filling member for filling a gap between the semiconductor chip and the wiring unit; and a film member for performing coating so as to cover one surface of each of the semiconductor chip, the filling member, and the wiring unit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.