Structures and methods for reducing stress in three-dimensional memory device
US11450770B2 · kind B2 · utility
0Cited by
5References
20Claims
0Family size
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Key dates
| Filing date | Nov 2, 2020 |
| Grant date | Sep 20, 2022 |
| Priority date | — |
| Expiry date | Nov 2, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0483
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments of counter-stress structures and methods for forming the same are disclosed. The present disclosure describes a semiconductor wafer including a substrate having a dielectric layer formed thereon and a device region in the dielectric layer. The device region includes at least one semiconductor device. The semiconductor wafer further includes a sacrificial region adjacent to the device region, wherein the sacrificial region includes at least one counter-stress structure configured to counteract wafer stress formed in the device region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.