System and method for performing sign-off timing analysis of electronic circuit designs
US11455450B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 3, 2021 |
| Grant date | Sep 27, 2022 |
| Priority date | — |
| Expiry date | Jun 3, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments include herein are directed towards a method for dynamic voltage and frequency scaling (DVFS) based timing signoff associated with an electronic design environment. Embodiments may include receiving, using a processor, an electronic design and specifying, via a graphical user interface, a voltage sweep for each power net associated with the electronic design. Embodiments may further include specifying, via the graphical user interface, at least one voltage sweep to be excluded from analysis. Embodiments may also include automatically generating DVFS configurations based upon, at least in part, the voltage sweep for each power net and the at least one voltage sweep to be excluded from analysis.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.