Write leveling a memory device using write DLL circuitry
US11456031B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 9, 2020 |
| Grant date | Sep 27, 2022 |
| Priority date | — |
| Expiry date | Jan 18, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2254
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A host device and memory device perform internal write leveling of a data strobe with a write command. The memory device includes an input-output interface that receives the data strobe from the host device. The memory device also includes internal write circuitry configured to launch an internal write signal. The internal write circuitry includes an emulation loop configured to emulate circuitry in a clock path of a write clock generated from the clock and used to generate a feedback clock. The internal write circuitry includes a write delay lock loop configured to receive the write clock and the feedback clock to determine a number of cycles used for the loop, transmit the number of cycles to the host device to be used as a cycle adjust in an internal write leveling process, and complete the internal write leveling process with the host device using the cycle adjust.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.