Architecture and processes to enable high capacity memory packages through memory die stacking

US11456281B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Yi Li · Chandler, US
• Zhiguo Qian · Chandler, US
• Prasad Ramanathan · Chandler, US
• Saikumar Jayaraman · Chandler, US
• Kemal Aygun · Tempe, US
• Hector Amador · Chandler, US
• Andrew Collins · Chandler, US
• Jianyong Xie · Chandler, US
• Shigeki Tomishima · Portland, US

Key dates

• Filing date: Sep 29, 2018
• Grant date: Sep 27, 2022
• Expiry date: Jan 28, 2041

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/18162
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Embodiments include electronic packages and methods of forming such packages. An electronic package includes a memory module comprising a first memory die. The first memory die includes first interconnects with a first pad pitch and second interconnects with a second pad pitch, where the second pad pitch is less than the first pad pitch. The memory module also includes a redistribution layer below the first memory die, and a second memory die below the redistribution layer, where the second memory die has first interconnects with a first pad pitch and second interconnects with a second pad pitch. The memory module further includes a mold encapsulating the second memory die, where through mold interconnects (TMIs) provide an electrical connection from the redistribution layer to mold layer. The TMIs may be through mold vias. The TMIs may be made through a passive interposer that is encapsulated in the mold.