Memory transistor with multiple charge storing layers and a high work function gate electrode
US11456365B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 25, 2021 |
| Grant date | Sep 27, 2022 |
| Priority date | — |
| Expiry date | May 22, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/693
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An example memory device includes a channel positioned between and electrically connecting a first diffusion region and a second diffusion region, and a tunnel dielectric layer, a multi-layer charge trapping layer, and a blocking dielectric layer disposed between the gate structure and the channel. The multi-layer charge trapping layer includes a first dielectric layer disposed abutting a second dielectric layer and an anti-tunneling layer disposed between the first and second dielectric layers. The anti-tunneling layer includes an oxide layer. The first dielectric layer includes oxygen-rich nitride and the second dielectric layer includes oxygen-lean nitride.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.