Chip package structure and manufacturing method thereof
US11462452B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 24, 2021 |
| Grant date | Oct 4, 2022 |
| Priority date | — |
| Expiry date | Jan 24, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/11
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A chip package structure including a chip, a stress buffer layer, a first insulating layer, a redistribution layer, a second insulating layer, and a solder ball is provided. The chip has an active surface, a back surface and a peripheral surface. The stress buffer layer covers the active surface and the peripheral surface, and the first insulating layer is disposed on the back surface. A bottom surface of the stress buffer layer is aligned with the back surface of the chip. The redistribution layer is electrically connected to the chip through an opening of the stress buffer layer. The second insulating layer covers the stress buffer layer and the redistribution layer. The solder ball is disposed in a blind hole of the second insulating layer and electrically connected to the redistribution layer. A top surface of the solder ball protrudes from an upper surface of the second insulating layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.