Chip bonding alignment structure, chip bonding structure and methods for fabricating the same
US11462513B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 22, 2021 |
| Grant date | Oct 4, 2022 |
| Priority date | — |
| Expiry date | Feb 22, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2225/06593
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A chip bonding alignment structure includes a semiconductor chip, a metal layer, an etching stop layer, at least one metal bump, a dielectric barrier layer, a silicon oxide layer, and a silicon carbonitride layer. The metal layer is disposed on a bonding surface of the semiconductor chip and has a metal alignment pattern. The etching stop layer covers the bonding surface and the metal layer. The metal bump extends upward from the metal layer and penetrates through the etching stop layer. The dielectric barrier layer covers the etching stop layer and the metal bump. The silicon oxide layer covers the dielectric barrier layer. The silicon carbonitride layer covers the silicon oxide layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.