Method and device for testing successive approximation register analog-to-digital converters
US11463098B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | Jun 8, 2021 |
| Grant date | Oct 4, 2022 |
| Priority date | — |
| Expiry date | Jun 8, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/46
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An integrated circuit includes a successive approximation register (SAR) analog-to-digital converter (ADC). The ADC includes a bit step selector. During testing of the ADC, the bit step selector selects a number of bits to be tested for a next analog test voltage based on digital values that are within an integer delta value of most recent digital value for a most recent analog test voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.