Apparatus and techniques for programming anti-fuses to repair a memory device
US11468965B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 11, 2019 |
| Grant date | Oct 11, 2022 |
| Priority date | — |
| Expiry date | Jan 8, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/883
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods, systems, and devices for programming anti-fuses are described. An apparatus may include a repair array including elements for replacing faulty elements in a memory array and may further include an array of anti-fuses for indicating which, if any, elements of the memory array are being replaced by elements within the repair array. The array of anti-fuses may indicate an address of an element of the memory array being replaced by an element within the repair array. The array of anti-fuses may indicate an enablement or disablement of the element within the repair array indicating whether the element within the repair array is enabled to replace the element of the memory array. The array of anti-fuses may include anti-fuses with lower reliability and anti-fuses with higher reliability. An anti-fuse associated with the enabling of the element within the repair array may include an anti-fuse having the higher reliability.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.