Patrick J. Mullarkey
86Patents
18h-index
28Co-inventors
84Inventor score
Filing activity: Dec 7, 1992 → Sep 11, 2024
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6378079B1 | Computer system having memory device with adjustable data clocking | Physics | 90 | Expired |
| US6365421B2 | Method and apparatus for storage of test results within an integrated circuit | Physics | 73 | Expired |
| US6194738A | Method and apparatus for storage of test results within an integrated circuit | Physics | 67 | Expired |
| US6327196A | Synchronous memory device having an adjustable data clocking circuit | Physics | 58 | Expired |
| US5631862A | Self current limiting antifuse circuit | Physics | 52 | Expired |
| US5264725A | Low-current polysilicon fuse | Electricity | 49 | Expired |
| US6556497B2 | Refresh controller and address remapping circuit and method for dual mode full/reduced density DRAMs | Physics | 48 | Expired |
| US6269451A | Method and apparatus for adjusting data timing by delaying clock signal | Physics | 47 | Expired |
| US6208577A | Circuit and method for refreshing data stored in a memory cell | Physics | 47 | Expired |
| US6499111B2 | Apparatus for adjusting delay of a clock signal relative to a data signal | Physics | 45 | Expired |
| US5627478A | Apparatus for disabling and re-enabling access to IC test functions | Physics | 36 | Expired |
| US6449203B1 | Refresh controller and address remapping circuit and method for dual mode full/reduced density DRAMs | Physics | 32 | Expired |
| US5732033A | Method and circuit for rapidly equilibrating paired digit lines of a memory device during testing | Physics | 29 | Expired |
| US6130834A | Circuit for programming antifuse bits | Physics | 28 | Expired |
| US6134137A | Rom-embedded-DRAM | Electricity | 26 | Expired |
| US6243285A | ROM-embedded-DRAM | Electricity | 24 | Expired |
| US5706238A | Self current limiting antifuse circuit | Physics | 23 | Expired |
| US5689455A | Circuit for programming antifuse bits | Physics | 18 | Expired |
| US6192446A | Memory device with command buffer | Physics | 17 | Expired |
| US6643789B2 | Computer system having memory device with adjustable data clocking using pass gates | Physics | 17 | Expired |
| US6373761B1 | Method and apparatus for multiple row activation in memory devices | Physics | 17 | Expired |
| US6459635B1 | Apparatus and method for increasing test flexibility of a memory device | Physics | 16 | Expired |
| US5900764A | Efficient Vccp supply with regulation for voltage control | Physics | 15 | Expired |
| US6519201B2 | Refresh controller and address remapping circuit and method for dual mode full/reduced density DRAMs | Physics | 15 | Expired |
| US6023434A | Method and apparatus for multiple row activation in memory devices | Physics | 15 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.