Semiconductor package with chip end design and trenches to control fillet spreading in stacked chip packages
US11469099B2 · kind B2 · utility
0Cited by
4References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 18, 2020 |
| Grant date | Oct 11, 2022 |
| Priority date | — |
| Expiry date | Jun 18, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/18161
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package includes a buffer, a chip stack mounted on the buffer, an adhesive layer disposed between the buffer and the chip stack, and a molding material surrounding the chip stack. The buffer includes a plurality of trenches disposed adjacent to a plurality of edges of the buffer. Each of the trenches is shorter than a corresponding adjacent edge of a chip area of the buffer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.