Semiconductor package having a redistribution layer for package-on-package structure
US11469148B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 12, 2019 |
| Grant date | Oct 11, 2022 |
| Priority date | — |
| Expiry date | Dec 31, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3511
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package includes: a frame having a cavity and including a wiring structure connecting first and second surfaces of the frame; a first connection structure on the first surface of the frame and including a first redistribution layer connected to the wiring structure; a first semiconductor chip on the first connection structure within the cavity; an encapsulant encapsulating the first semiconductor chip and covering the second surface of the frame; a second connection structure including a second redistribution layer including a first redistribution pattern and first connection vias; and a second semiconductor chip disposed on the second connection structure and having connection pads connected to the second redistribution layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.