Patent · US Active

Space efficient and low parasitic half bridge

US11469164B2 · kind B2 · utility

1Cited by

0References

18Claims

0Family size

Assignee

Infineon Technologies AG · DE

Inventors

Robert Fehler · Regensburg, DE
Eung San Cho · Torrance, US
Danny Clavette · Greene, US
Petteri Palm · Regensburg, DE

Key dates

Filing date	Jan 16, 2020
Grant date	Oct 11, 2022
Priority date	—
Expiry date	Oct 17, 2040

Classification

Technology area (CPC H)Electricity
CPC primaryH01L2924/19105
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

A packaged half-bridge circuit includes a carrier having a dielectric core and a first layer of metallization formed on an upper surface of the carrier, first and second semiconductor chips, each including a first terminal, a second terminal, and a control terminal, and a conductive connector mounted on the upper surface of the carrier and electrically connected to the first layer of metallization. The first semiconductor chip is configured as a high-side switch of the half-bridge circuit. The second semiconductor chip is configured as a low-side switch of the half-bridge circuit. At least one of the first and second semiconductor chips is embedded within the dielectric core of the carrier. The conductive connector is electrically connected to one of the first and second terminals from one or both of the first and second semiconductor chips.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.