Semiconductor device having reduced contact resistance between access transistors and conductive features and method of manufacturing the same
US11469234B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 13, 2020 |
| Grant date | Oct 11, 2022 |
| Priority date | — |
| Expiry date | Nov 13, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/488
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present disclosure provides a semiconductor device. The semiconductor device includes a substrate, a storage capacitor, an access transistor, and at least one conductive feature for electrically coupling the storage capacitor to the access transistor. The substrate includes at least one isolation feature defining a plurality of active regions, wherein a plurality of impurity regions of the access transistor are in the active region. The storage capacitor is disposed over the substrate, and the conductive feature extends from the storage capacitor and into a portion of the substrate where one of the impurity regions is disposed. As a result, a contact area between the access transistor and the conductive feature is increased, and an operation speed of the compact semiconductor device is increased.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.