Cache program operation of three-dimensional memory device with static random-access memory
US11474739B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 27, 2019 |
| Grant date | Oct 18, 2022 |
| Priority date | — |
| Expiry date | Jun 27, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/40
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments of three-dimensional (3D) memory devices with a 3D NAND memory array having a plurality of pages, an on-die cache coupled to the memory array on a same chip and configured to cache a plurality of batches of program data between a host and the memory array, the on-die cache having SRAM cells, and a controller coupled to the on-die cache on the same chip. The controller is configured to check a status of an (N−2)th batch of program data, N being an integer equal to or greater than 2, program an (N−1)th batch of program data into respective pages in the 3D NAND memory array, and cache an Nth batch of program data in respective space in the on-die cache as a backup copy of the Nth batch of program data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.