Memory and memory system
US11475936B2 · kind B2 · utility
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17Claims
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Key dates
| Filing date | Jul 27, 2020 |
| Grant date | Oct 18, 2022 |
| Priority date | — |
| Expiry date | Sep 25, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4085
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory includes a plurality of rows, each of which is coupled to a plurality of memory cells; a target row determining circuit suitable for determining a row that is likely to lose data among the plurality of rows as a target row; and a transfer circuit suitable for transferring, when a number of target rows determined by the target row determining circuit is equal to or greater than a threshold value, information representing that the number of target rows reaches the threshold value to a memory controller.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.